The present invention pertains to memory expansion and more particularly to expansion of a microprocessor's directly addressable memory range.
With the widespread usage of microprocessors to perform such operations as switching control in small remotely located digital multiplexer systems, sufficient memory for storing program code instructions and data becomes a limiting factor in system design. Commonly used microprocessors are those such as the Intel 8085 and Intel 8086 models. Such microprocessors are limited to 64K of directly addressable memory for both program code instructions and data.
The solution to this problem is to expand memory. A common implementation of this solution employs the use of the microprocessor's I/O ports. This solution also requires a change in the implementation of the system software. This solution dictates that an I/O instruction be executed before the memory read or write and also after the memory read or write. As a result each memory access instruction must now be prefixed and suffixed by I/O instruction. This in itself increases the need for memory by requiring 3 times as many instructions for each memory read or write instruction.
In addition, for systems which many memory accesses are made, the real time of the system through-put is greatly effected. Therefore, the use of I/O ports creates as many or more problems then it solves.
The present invention is a circuit which allows the expansion of memory without the use of I/O ports. This circuit is a fast response time circuit which has no adverse effects on system real time. This circuit decodes operation codes and status bits of the microprocessor during each processor cycle. This circuit then determines which bank of memory is required for the particular processor access (program code instruction or data). Further, this circuit offers the advantage in that it does not require any changes to the system software. This invention is implemented on a 1500 gate, 5 micron CMOS gate array.